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XADC

XADC

Project name：XADC Usage.

Specific requirements：Implement the xadc's ip core to collect input data and output the sampling results.

System Design： The Artix-7 series FPGA contains two 12-bit, 1 MSPS analog-to-digital converters that can be configured to sample two external analog channels simultaneously. The development board uses an on-chip reference voltage of 1.25 V for the AD sampling part, and the on-chip reference voltage has good stability. p1 high-speed socket contains two pairs of high-speed differential input AD sampling; p2 is Arduino compatible and contains six single-ended inputs or six pairs of differential input AD sampling.

Implementation process：

  1. initialize the ip core of xadc and connect the development board.

  2. Open the vivado file for comprehensive download, download the jtag with the connection, and double-click on the Xadc in the figure.

  1. open and add the data to be tested, at this time the A5 pin is connected to the external voltage, the input voltage 2.0 volts test result is shown in the figure: (VAUXP1_VAUXP2 is the corresponding channel), because the circuit diagram uses voltage division, so the test result is 3.32 parts per million of the voltage under test.

The correspondence between the ad channels in the development version and the development version is shown below.