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This development board is equipped with a high-speed DDR3 SDRAM, model: MT41J128M16JT-093, capacity: 256MByte (128M*16bit), 16bit bus. The FPGA and DDR3 SDRAM on the development board are connected to the BANK35 IO. The DDR3 hardware design requires strict consideration of signal integrity, and we have fully considered matching resistors/termination resistors, alignment impedance control, and alignment equal length control during the circuit design and PCB design to ensure the high speed and stable operation of DDR3.


Specific requirements:implement DDR3 data reading and writing.

System design:

Implementation process:

1.After creating a new project, open Create Block Design, and modify the Design name.

2.Add IPs and complete the connection according to the system design.

3.Follow the diagram below to configure the IP accordingly.

Axi Datamover Configuration:

mig_7_series Configuration:

After opening the IP, click NEXT to enter the configuration interface.

After selecting the model, click NEXT and select DDR3 SDRAM:

Click NEXT to continue with the configuration as follows.:

Then click NEXT to configure as follows.

Click on validate and then click next to finish.

Open the project and compile the board, then use ILA to capture the data, first control the write data, then read the data to determine if it is correct.

  1. The write data is 123456789_123456789_123456789_12345。

  1. The read data is the same as the write.