SoC implementation of Wujian100

Purpose

Mainly complete the deployment of wujian100 SoC on FPGA. Learn to use Xilinx vivado tools.

Experimental procedure

1. Open wujian100 with Vivado

1) Create project

Add the verilog source code after next:

Add the xdc file after clicking next

Choose a development board

2) After the file is added, VIVADO will automatically identify, compile, and analyze it. VIVADO analyzes the error in the file and marks it with a red wavy line (the reason for the error is that the header file is not recognized, and the four file types can be changed to the header file type)

3) call clock IP

2. Add pin constraints according to the perfv board manual

See the document "Changes to xdc" for details.

3. Comprehensive project, download bit stream after the synthesis is correct

There may be an error - a certain module is not found, just comment out this module

The combined results are as follows:

4. Download to the development board

1) Interface to connect computer and development board

2) Cure FLASH

Display 5 indicates that wujian100 has been downloaded to the development board, and it can run after power-on reset.